1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and more particularly, to a semiconductor integrated circuit device having an edge trigger type flip-flop circuit for decreasing delay time.
2. Description of the Related Art
Generally, in a large scale integration circuit such as a gate array circuit, and the like, an edge trigger type flip-flop circuit has been employed as a latch circuit, and the like. In the prior art, an edge trigger type flip-flop circuit (semiconductor integrated circuit device) having four three-inputs NAND gates and a latch circuit (flip-flop circuit) has been provided, for example, Japanese Unexamined Patent Publication No. 57-68929, to prevent a hazard on complementary output terminals when presetting the semiconductor integrated circuit device. Nevertheless, this edge trigger type flip-flop circuit of JPP'929 has a problem in that a load capacitance connected to an output of the flip-flop circuit influences the delay time of the other output (inverted output) of the flip-flop circuit. Note, this problem is important in a semiconductor integrated circuit device constituted by CMOS or Bi-CMOS circuits, as the CMOS and Bi-CMOS circuits do not have a large driving power.
Therefore, in recent years, an edge trigger type flip-flop (semiconductor integrated circuit device) having delay compensation gates connected to both outputs (complementary outputs) thereof has also been provided to compensate for the delay time. Namely, the semiconductor integrated circuit device (edge trigger type flip-flop circuit) comprises a preceding circuit portion, a flip-flop circuit portion, and a compensation circuit portion. The compensation circuit portion includes two inverters to thereby decrease the difference between the delay times caused by different values of load capacitance at the output and inverted output of the flip-flop circuit portion. Nevertheless, in the edge trigger type flip-flop having the delay compensation circuit portion, the delay time becomes long and the operation speed becomes slow. Note, in semiconductor integrated circuit devices, high speed operation, in accordance with the development of semiconductor device technology, has been also required.